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esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 1/28 sdram 512k x 16bit x 2banks synchronous dram features z jedec standard 3.3v power supply z lvttl compatible with multiplexed address z dual banks operation z mrs cycle with address key programs - cas latency (2 & 3 ) - burst length (1, 2, 4, 8 & full page) - burst type (sequential & interleave) z all inputs are sampled at the positive going edge of the system clock z burst read single-bit write operation z dqm for masking z auto & self refresh z 32ms refresh period (2k cycle) general description the m12l16161a is 16,777,216 bits synchronous high data rate dynamic ram organized as 2 x 524,288 words by 16 bits, fabricated with high performance cmos technology. synchronous design allows precise cycle control with the use of system clock i/o transacti ons are possible on every clock cycle. range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. ordering information product id max freq. package comments M12L16161A-5TG2Q 200mhz tsop(ii) pb-free m12l16161a-7tg2q 143mhz tsop(ii) pb-free pin configuration (top view) (tsopii 50l, 400milx825mil body, 0.8mm pin pitch) v dd dq0 dq1 v ssq dq2 dq3 v ddq dq4 dq5 v ssq dq6 dq7 v ddq ldqm we cas ras cs ba a10/ap a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 v ss dq15 dq14 v ssq dq13 dq12 v ddq dq11 dq10 v ssq dq9 dq8 v ddq n.c/rfu udqm clk cke n.c a9 a8 a7 a6 a5 a4 v ss 50pin tsop(ii) (400mil x 825mil) (0.8 mm pin pitch)
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 2/28 functional block diagram pin function description pin name input function clk system clock active on the positive going edge to sample all inputs. cs chip select disables or enables device operation by masking or enabling all inputs except clk, cke and l(u)dqm. cke clock enable masks system clock to freeze operation from the next clock cycle. cke should be enabled at least one cycle prior to new command. disable input buffers for power down in standby. a0 ~ a10/ap address row / column addresses are multiplexed on the same pins. row address : ra0 ~ ra10, column address : ca0 ~ ca7 ba bank select address selects bank to be activated during row address latch time. selects bank for read/write during column address latch time. ras row address strobe latches row addresses on the positive going edge of the clk with ras low. enables row access & precharge. cas column address strobe latches column addresses on the pos itive going edge of the clk with cas low. enables column access. we write enable enables write operation and row precharge. latches data in starting from cas , we active. l(u)dqm data input / output mask makes data output hi-z, t shz after the clock and masks the output. blocks data input when l(u)dqm active. dq0 ~ 15 data input / output data inputs/outputs are multiplexed on the same pins. vdd/vss power supply/ground power and ground for the input buffers and the core logic. vddq/vssq data output power/ground isolated power supply and ground for the ou tput buffers to provide improved noise immunity. n.c/rfu no connection/ reserved for future use this pin is recommended to be left no connection on the device. bank select data input register column decoder latency & burst length programming register 512k x 16 512k x 16 timing register clk cke cs ras cas we l(u)dqm ldqm lwcbr dqi ldqm lwe lras lcbr lwe lcas clk add lcke address register row buffer refresh counter row decoder sense amp col. buffer lras lcbr i/o control output buffer
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 3/28 absolute maximum ratings parameter symbol value unit voltage on any pin relative to v ss v in ,v out -1.0 ~ 4.6 v voltage on v dd supply relative to v ss v dd ,v ddq -1.0 ~ 4.6 v operating ambient temperature t a 0 ~ 70 c storage temperature t stg -55 ~ + 150 c power dissipation p d 0.7 w short circuit current i os 50 ma note: permanent device damage may occur if abso lute maximum ratings are exceeded. functional operation should be restrict ed to recommended operating condition. exposure to higher than recommended voltage for exten ded periods of time could affect device reliability. dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v) parameter symbol min typ max unit note supply voltage v dd ,v ddq 3.0 3.3 3.6 v input logic high voltage v ih 2.0 3.0 v dd +0.3 v 1 input logic low voltage v il -0.3 0 0.8 v 2 output logic high voltage v oh 2.4 - - v i oh =-2ma output logic low voltage v ol - - 0.4 v i ol = 2ma input leakage current i il -5 - 5 ua 3 output leakage current i ol -5 - 5 ua 4 note: 1.v ih (max) = 4.6v ac for pulse width 10ns acceptable. 2.v il (min) = -1.5v ac for pulse width 10ns acceptable. 3.any input 0v v in v dd , all other pins are not under test = 0v. 4.dout is disabled, 0v v out v dd . capacitance (v dd = 3.3v, t a = 25 c , f = 1mhz) pin symbol min max unit clock c clk 2.5 4.0 pf ras , cas , we , cs , cke, ldqm, udqm c in 2.5 5.0 pf address c add 2.5 5.0 pf dq0 ~dq15 c out 4.0 6.5 pf
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 4/28 dc characteristics (recommended operating condition unless otherwise noted, v ih (min)/v il (max)=2.0v/0.8v) version parameter symbol test condition cas latency -5 -7 unit note operating current (one bank active) i cc1 burst length = 1 t rc t rc (min), t cc t cc (min), i ol = 0ma 100 80 ma 1 i cc2p cke v il (max), t cc =15ns 2 precharge standby current in power-down mode i cc2ps cke v il (max), clk v ih (min), cs v ih (min), t cc =15ns input signals are changed one time during 30ns 25 ma precharge standby current in non power-down mode i cc2ns cke v ih (min), clk v il (max), t cc =15ns 10 active standby current in power-down mode i cc3ps cke v il (max), clk v ih (min), cs v ih (min), t cc =15ns input signals are changed one time during 2clks all other pins v dd -0.2v or 0.2v 25 ma active standby current in non power-down mode (one bank active) i cc3ns cke v ih (min), clk t rfc (min) 100 80 ma 2 self refresh current i cc6 cke 0.2v 1 ma note: 1.measured with outputs open. addresse s are changed only one time during t cc (min). 2.refresh period is 32ms. addresses are changed only one time during t cc (min).
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 5/28 ac operating test conditions (v dd =3.3v parameter value unit input levels (vih/vil) 2.4 / 0.4 v input timing measurement reference level 1.4 v input rise and fall time tr / tf = 1 / 1 ns output timing measurement reference level 1.4 v output load condition see fig.2 operating ac parameter (ac operating conditions unless otherwise noted) version parameter symbol -5 -7 unit note row active to row active delay t rrd (min) 10 14 ns 1 ras to cas delay t rcd (min) 15 20 ns 1 row precharge time t rp (min) 15 20 ns 1 t ras (min) 30 42 ns 1 row active time t ras (max) 100 us @operating t rc (min) 48 63 ns 1 row cycle time @auto refresh t rfc (min) 55 63 ns 1, 5 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to row precharge t rdl (min) 2 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 3 cas latency=3 2 number of valid output data cas latency=2 1 ea 4 note: 1. the minimum number of clock cycles is determined by divi ding the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. all parts allow every cycle column address change. 4. in case of row precharge interr upt, auto precharge and read burst stop. the earliest a precharge command can be issued after a re ad command without the loss of data is cl+bl-2 clocks. 5. a new command may be given t rfc after self refresh exit. 3.3v output (fig.2) ac output load circuit 30 pf vtt =1.4v voh(dc) = 2.4v, ioh = -2ma vol(dc) = 0.4v, iol = 2ma 30 pf output (fig.1) dc output load circuit z0=50 ? 870 ? 1200 ? 50
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 6/28 ac characteristics (ac operating conditions unless otherwise noted) -5 -7 parameter symbol min max min max unit note cas latency =3 5 7 clk cycle time cas latency =2 t cc 7 1000 8.6 1000 ns 1 cas latency =3 - 4.5 - 6 clk to valid output delay cas latency =2 t sac - 5 - 6 ns 1 output data hold time t oh 2 2 ns 2 clk high pulse width t ch 2 2 ns 3 clk low pulse width t cl 2 2 ns 3 input setup time t ss 2 2 ns 3 input hold time t sh 1 1 ns 3 clk to output in low-z t slz 1 1 ns 2 cas latency =3 - 4.5 - 6 clk to output in hi-z cas latency =2 t shz - 5 - 6 ns *all ac parameters are measured from half to half. note: 1.parameters depend on programmed cas latency. 2.if clock rising time is longer than 1ns,(t r/2-0.5)ns should be added to the parameter. 3.assumed input rise and fall time (tr & tf)=1ns. if tr & tf is longer than 1ns, transient time compensation shoul d be considered, i.e., [(tr+ tf)/2-1]ns should be added to the parameter.
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 7/28 mode register ba a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 1 jedec standard test set (refresh counter test) ba a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 x x 1 0 0 ltmode wt bl burst read and single write (for write through cache) ba a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 0 use in future ba a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 x x x 1 1 v v v v v v v vender specific ba a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 v =valid 0 0 0 0 0 ltmode wt bl mode register set x =don?t care bit2-0 wt=0 wt=1 000 1 1 001 2 2 010 4 4 011 8 8 100 r r 101 r r 110 r r burst length 111 full page r 0 sequential wrap type 1 interleave bits6-4 cas latency 000 r 001 r 010 2 011 3 100 r 101 r 110 r latency mode 111 r remark r : reserved mode register write timing mode register write clock cke cs ras we a0-a10, ba cas
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 8/28 burst length and sequence (burst of two) starting address (column address a0 binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 0 0,1 0,1 1 1,0 1,0 (burst of four) starting address (column address a1-a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 00 0,1,2,3 0,1,2,3 01 1,2,3,0 1,0,3,2 10 2,3,0,1 2,3,0,1 11 3,0,1,2 3,2,1,0 (burst of eight) starting address (column address a2-a0, binary) sequential addressing sequence (decimal) interleave addressing sequence (decimal) 000 0,1,2,3,4,5,6,7 0,1,2,3,4,5,6,7 001 1,2,3,4,5,6,7,0 1,0,3,2,5,4,7,6 010 2,3,4,5,6,7,0,1 2,3,0,1,6,7,4,5 011 3,4,5,6,7,0,1,2 3,2,1,0,7,6,5,4 100 4,5,6,7,0,1,2,3 4,5,6,7,0,1,2,3 101 5,6,7,0,1,2,3,4 5,4,7,6,1,0,3,2 110 6,7,0,1,2,3,4,5 6,7,4,5,2,3,0,1 111 7,0,1,2,3,4,5,6 7,6,5,4,3,2,1,0 full page burst is an extension of the above tables of sequential addressing, with the length being 256 for 1mx16 device. power up sequence 1.apply power and start clock, attempt to maintain cke= ?h?, l(u)dqm = ?h? and the other pin are nop condition at the inputs. 2.maintain stable power, stable clock and nop input condition for a minimum of 200us. 3.issue precharge commands for all banks of the devices. 4.issue 2 or more auto-refresh commands. 5.issue mode register set command to initialize the mode register. cf.)sequence of 4 & 5 is regardless of the order.
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 9/28 simplified truth table command cken-1 cken cs ras cas we dqm ba a10/ap a9~a0 note register mode register set h x l l l l x op code 1,2 auto refresh h 3 entry h l l l l h x x 3 l h h h 3 refresh self refresh exit l h h x x x x x 3 bank active & row addr. h x l l h h x v row address auto precharge disable l 4 read & column address auto precharge enable h x l h l h x v h column address (a0~a7) 4,5 auto precharge disable l 4 write & column address auto precharge enable h x l h l l x v h column address (a0~a7) 4,5 burst stop h x l h h l x x 6 bank selection v l 4 precharge both banks h x l l h l x x h x 4 h x x x entry h l l h h h x clock suspend or active power down exit l h x x x x x x h x x x entry h l l h h h x h x x x precharge power down mode exit l h l h h h x x dqm h x v x 7 h h x x x no operation command h x l h h h x x (v= valid, x= don?t care, h= logic high, l = logic low) note: 1. op code: operation code a0~ a10/ap, ba: program keys.(@mrs) 2. mrs can be issued only at both banks precharge state. a new command can be issued after 2 clock cycle of mrs. 3. auto refresh functions are as same as cbr refresh of dram. the automatical precharge without row pr echarge command is meant by ?auto?. auto / self refresh can be issued only at both banks idle state. 4. ba: bank select address. if ?low?: at read, write, row active and precharge, bank a is selected. if ?high?: at read, write, row active and precharge, bank b is selected. if a10/ap is ?high? at row precharge, ba ignored and both banks are selected. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read /write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at positive go ing edge of a clk masks the data-in at the very clk (w rite dqm latency is 0), but makes hi-z state the data-out of 2 clk cycles after. (read dqm latency is 2)
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 10/28 single bit read-write-read cycle (same page) @ cas latency=3, burst length=1 : d o n ' t c a r e 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cs ras cas addr we dq dqm a10/ap t ch t cl t cc row active ba *note1 high t rcd t ss t ss t sh t sh t ss t sh t ss t ss t sh t ss t ss t sh ra ca cb cc rb bs bs bs bs bs bs ra qa db qc rb read write read precharge row active t rc t ras t rp t ccd t rac *note2 *note2,3 *note4 *note2 *note2,3 *note 3 *note 3 *note2,3 t sh t slz t sac t oh t sh t sh t ss *note4 *note 3
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 11/28 *note: 1. all inputs expect cke & dqm can be don?t care when cs is high at the clk high going edge. 2. bank active & read/write are controlled by ba. ba active & read/write 0 bank a 1 bank b 3.enable and disable auto precharge function are controlled by a10/ap in read/write command. a10/ap ba operation 0 disable auto precharge, leave bank a active at end of burst. 0 1 disable auto precharge, leave bank b active at end of burst. 0 enable auto precharge, precha rge bank a at end of burst. 1 1 enable auto precharge, precha rge bank b at end of burst. 4.a10/ap and ba control bank precharge when precharge command is asserted. a10/ap ba precharge 0 0 bank a 0 1 bank b 1 x both banks
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 12/28 power up sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke addr dq dqm a10/ap t rp key raa raa precharge all banks auto refresh auto refresh mode register set (a-bank) row active : don't care t rfc t rfc high level is necessary high level is necessary ba high-z cs ras cas we key key
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 13/28 read & write cycle at same bank @ burst length = 4 t rcd t rc clock cke cs ras cas addr dqm ba cl=2 cl=3 ra rb cb0 t oh t sac t shz t shz t rdl read row active precharge (a-bank) (a-bank) precharge (a-bank) (a-bank) write (a-bank) row active (a-bank) *note3 *note3 *note4 *note4 :don'tcare *note1 qa0 qa1 qa2 qa3 db0 db3 db1 db2 qa0 qa1 qa2 qa3 db0 db3 db1 db2 t rac t rac t rdl ca0 a10/ap ra rb high *note2 we t oh t sac qc 012 345 678910111213141516171819 *note: 1.minimum row cycle times is required to complete internal dram operation. 2.row precharge can interrupt burst on any cycle. [cas latency-1] number of valid output data is available after row precharge. last valid output will be hi-z(t shz ) after the clock. 3.access time from row active command. tcc*(t rcd +cas latency-1)+t sac 4.output will be hi-z after the end of burst.(1,2,4,8 bit burst) burst can?t end in full page mode.
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 14/28 page read & write cycle at same bank @ burst length=4 *note: 1.to write data before burst read ends, dqm should be asserted three cycles prior to write command to avoid bus contention. 2.row precharge will interrupt writing. last data input, t rdl before row precharge, will be written. 3.dqm should mask invalid input data on precharge command cycle when asserting precharge before end of burst. input data after row precharge cycle will be masked internally. clock cke cs ras cas ba addr a10/ap cl=2 cl=3 we dqm high t rcd *note2 ra ca0 cb0 cc0 cd0 ra qa0 qa1 qb0 qb1 qb2 dc0 dc1 dd0 dd1 qa0 qa1 qb0 qb1 dc0 dc1 dd0 dd2 t cdl *note1 row active (a-bank) read (a-bank) read (a-bank) write (a-bank) write (a-bank) precharge (a-bank) : don't care dq 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 t rdl *note3
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 15/28 page read cycle at different bank @ burst length=4 *note: 1. cs can be don?t cared when ras , cas and we are high at the clock high going edge. 2.to interrupt a burst read by row precharge, both the read and the precharge banks must be the same. clock cke cs ras cas ba addr a10/ap cl=2 cl=3 we dqm high *note2 raa caa rbb raa read (a-bank) row active row active (b-bank) (a-bank) read (a-bank) read (b-bank) read (a-bank) read (b-bank) precharge (a-bank) : don't care dq cbb cac cbd cae qaa0 *note1 rbb 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 qaa1 qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qac0 qac1 qbd0 qbd1 qae0 qae1 qaa0 qaa1 qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qac0 qac1 qbd0 qbd1 qae0 qae1
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 16/28 page write cycle at different bank @ burst length = 4 *note: 1.to interrupt burst write by row precharge, dqm should be asserted to mask invalid input data. 2.to interrupt burst write by row precharge, both the write and the precharge banks must be the same. clock cke cs ras cas ba addr a10/ap we dqm high row active (a-bank) row active (b-bank) write (a-bank) precharge (both banks) : don't care dq write (a-bank) write (b-bank) write (b-bank) daa0 daa1 daa2 daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 dbd0 dbd1 raa rbb raa caa rbb cbb cac cbd *note2 t cdl t rdl *note1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 17/28 read & write cycle at different bank @ burst length = 4 *note: 1.t cdl should be met to complete write.
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 18/28 read & write cycle with auto precharge @ burst length =4 *note: 1.t cdl should be controlled to meet minimum t ras before internal precharge start (in the case of burst length=1 & 2 and brsw mode) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clock cke cas addr we dq dqm a10/ap ba cl=2 cl=3 row active ( a - bank ) row active ( b - bank ) read with auto precharge ( a - bank ) auto precharge start point (b-bank) : d o n ' t c a r e qa1 qa2 qa3 db1 db2 db3 db0 qa0 ra cb ra ca rb rb qa1 qa2 qa3 db1 db2 db3 db0 qa0 write with auto precharge (b-bank) high auto precharge start point ( a - bank) cs ras
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 19/28 clock suspension & dqm operation cycle @ cas latency=2, burst length=4 *note: 1.dqm is needed to prevent bus contention. clock cke addr dq dqm a10/ap ra ca cb cc ra qa0 qa1 qa2 qa3 t shz qb1 qb0 t shz dc0 dc2 *note1 row active read clock suspension read read dqm write write dqm clock suspension write dqm :don't care ba cs ras cas we 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 20/28 read interrupted by precharge command & read burst stop cycle @ burst length=full page *note: 1.burst can?t end in full page mode, so auto precharge can?t issue. 2.about the valid dqs after burst stop, it is same as the case of ras interrupt. both cases are illustrated above timing diagram. see the label 1,2 on them. but at burst write, burst stop and ras interrupt should be compared carefully. refer the timing diagram of ?full page write burst stop cycle?. 3.burst stop is valid at every burst length. clock cke addr dq dqm a10/ap ba raa caa cab raa qaa0 qaa1 qab1 qab0 qab2 *note1 row active (a-bank) read (a-bank) burst stop read (a-bank) :don't care high cl=2 cl=3 qaa2 qaa3 qaa4 qab3 qab4 qab5 qaa0 qaa1 qab1 qab0 qab2 qaa2 qaa3 qaa4 qab3 qab4 qab5 1 1 2 2 precharge (a-bank) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cs ras cas we *note2
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 21/28 write interrupted by precharge command & write burst stop cycle @ burst length=full page *note: 1. burst can?t end in full page mode, so auto precharge can?t issue. 2.data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. it is defined by ac parameter of t rdl . dqm at write interrupted by precharge command is needed to prevent invalid write. input data after row precharge cycle will be masked internally. 3.burst stop is valid at every burst length. clock cke addr dq dqm a10/ap raa caa cab raa daa0 daa1 dab1 dab0 dab2 row active (a-bank) write (a-bank) burst stop write (a-bank) :don't care high daa2 daa3 daa4 dab3 dab4 dab5 precharge (a-bank) t bdl t rdl *note2 cs ras cas we ba 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 22/28 burst read single bit write cycle @ burst length=2 *note: 1.brsw modes is enabled by setting a9 ?high? at mrs(mode register set). at the brsw mode, the burst length at write is fixed to ?1? regardless of programmed burst length. 2.when brsw write command with auto precharge is executed, keep it in mind that t ras should not be violated. auto precharge is executed at the next cycle of burst-end, so in the case of brsw write command, the precharge command will be issued after two clock cycles. clock cke addr cl=2 dqm a10/ap ba raa rac raa qab0 row active (a-bank) write (a-bank) :don't care high qab1 precharge (a-bank) caa rbb cab cbc cad rac dbc0 dq daa0 qab0 dbc0 qab1 cl=3 row active (b-bank) row active (a-bank) write with auto precharge (b-bank) read (a-bank) daa0 qad0 qad1 qad0 qad1 *note1 cs ras cas we rbb *note2 read with auto precharge (a-bank)
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 23/28 active/precharge power down mode @ cas latency=2, burst length=4 *note: 1.both banks should be in idle state prior to entering precharge power down mode. 2.cke should be set high at least 1clk+tss prior to row active command. 3.can not violate minimum refresh specification. (32ms) clock cke addr dq dqm a10/ap active power-down exit precharge : don't care *note3 *note2 *note1 t ss ra ra qa0 qa1 qa2 t shz precharge power-down entry precharge power-down exit row active active power-down entry read 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 ca ba ras cas cs we t ss t ss
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 24/28 self refresh entry & exit cycle clock cke addr dq dqm a10/ap self refresh entry auto refresh :don'tcare self refresh exit hi-z hi-z we ba cas ras cs *note2 *note1 *note4 t rfcmin *note6 *note5 *note7 0 1 2 3 4 5 6 7 8 9 101112 13 1415 16 171819 t ss *note3 *note: to enter self refresh mode 1. cs , ras & cas with cke should be low at the same clock cycle. 2. after 1 clock cycle, all the inputs including the system clock can be don?t care except for cke. 3. the device remains in self refresh mode as long as cke stays ?low?. cf.) once the device enters self refresh mode, minimum t ras is required before exit from self refresh. to exit self refresh mode 4. system clock restart and be stable before returning cke high. 5. cs starts from high. 6. minimum t rfc is required after cke going high to complete self refresh exit. 7. 2k cycle of burst auto refresh is required immediately before self refresh entry and immediately after self refresh exit.
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 25/28 mode register set cycle auto refresh cycle clock cke addr key :don't care high cs ras cas high *note3 ra *note1 dq hi-z dqm 123456 012345678910 hi-z *note2 t rfc mrs new command auto refresh new command we 0 *both banks precharge should be completed before mode register set cycle and auto refresh cycle. mode register set cycle *note: 1. cs , ras , cas & we activation at the same clock cycle with address key will set internal mode register. 2.minimum 2 clock cycles should be met before new ras activation. 3.please refer to mode register set table.
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 26/28 package dimensions 50-lead tsop(ii) sdram(400mil) "a" seating plane y gage plane base metal with plating l detail "a" section y-y b b1 c1 c e e1 d 1 y e y a1 a2 a 25 50 26 l1 dimension in mm dimension in inch symbol min nom max min nom max a - - 1.20 - - 0.047 a1 0.051 0.127 0.203 0.002 0.005 0.008 a2 0.95 1.00 1.05 0.037 0.039 0.041 b 0.30 - 0.45 0.012 - 0.018 b1 0.30 0.35 0.40 0.012 0.014 0.016 c 0.12 - 0.21 0.005 - 0.008 c1 0.10 0.127 0.16 0.004 0.005 0.006 d 20.82 20.95 21.08 0.820 0.825 0.830 e 11.56 11.76 11.96 0.455 0.463 0.471 e1 10.03 10.16 10.29 0.394 0.400 0.405 l 0.40 0.50 0.60 0.016 0.020 0.024 l1 0.80 ref 0.031 ref e 0.80 bsc 0.031 bsc y - - 0.1 - - 0.004 0 - 8 0 - 8 controlling dimension : millimeter
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 27/28 revision history revision date description 0.1 2011.03.25 original 1.0 2011.09.27 1. delete ?preliminary? 2. modify the specification of t oh
esmt m12l16161a (2q) elite semiconductor memory technology inc. publication date : sep. 2011 revision : 1.0 28/28 important notice all rights reserved. no part of this document may be rep roduced or duplicated in any form or by any means without the prior permission of esmt. the contents contained in this document are believed to be accurate at the time of publication. esmt assumes no responsibility for any error in this document, and reserves the ri ght to change the product s or specification in this document without notice. the information contained herein is pres ented only as a guide or examples for the application of our products. no responsibility is assumed by esmt for any infringement of patents, copyrights , or other intellectual property rights of third parties which may result from its use. no license, either express , implied or otherwise, is granted un der any patents, copy rights or other intellectual property righ ts of esmt or others. any semiconductor devices may have inher ently a certain rate of failure. to minimize risks associated with cust omer's application, adequate design and operating safeguards against injury, dam age, or loss from such failure, should be provided by the custom er when making application designs. esmt's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affe ct human lives or cause physical injury or property damage. if products described here are to be used for such kinds of application, purchaser must do its ow n quality assurance testing appropriate to such applications.

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